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lt1809/lt1810 1 180910fa typical application description single/dual 180mhz, 350v/s rail-to-rail input and output low distortion op amps the lt ? 1809/lt1810 are single/dual low distortion rail-to- rail input and output op amps with a 350v/s slew rate. these ampli? ers have a C3db bandwidth of 320mhz at unity-gain, a gain-bandwidth product of 180mhz (a v 10) and an 85ma output current to ? t the needs of low voltage, high performance signal conditioning systems. the lt1809/lt1810 have an input range that includes both supply rails and an output that swings within 20mv of either supply rail to maximize the signal dynamic range in low supply applications. the lt1809/lt1810 have very low distortion (C90dbc) up to 5mhz that allows them to be used in high performance data acquisition systems. the lt1809/lt1810 maintain their performance for supplies from 2.5v to 12.6v and are speci? ed at 3v, 5v and 5v supplies. the inputs can be driven beyond the supplies without damage or phase reversal of the output. the lt1809 is available in the 8-pin so package with the standard op amp pinout and the 6-pin sot-23 package. the lt1810 features the standard dual op amp pinout and is available in 8-pin so and msop packages. these devices can be used as a plug-in replacement for many op amps to improve input/output range and performance. high speed adc driver features applications n C3db bandwidth: 320mhz, a v = 1 n gain-bandwidth product: 180mhz, a v 10 n slew rate: 350v/s n wide supply range: 2.5v to 12.6v n large output current: 85ma n low distortion, 5mhz: C 90dbc n input common mode range includes both rails n output swings rail-to-rail n input offset voltage, rail-to-rail: 2.5mv max n common mode rejection: 89db typ n power supply rejection: 87db typ n open-loop gain: 100v/mv typ n shutdown pin: lt1809 n single in 8-pin so and 6-pin sot-23 packages n dual in 8-pin so and msop packages n operating temperature range: C40c to 85c n low pro? le (1mm) sot-23 (thinsot?) package n driving a/d converters n low voltage signal processing n active filters n rail-to-rail buffer ampli? ers n video line driver l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. thinsot is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. distortion vs frequency C + lt1809 ltc ? 1420 pga gain = 1 ref = 2.048v 5v 5v 12 bits 10msps C5v C5v ? ? ? r2 1k r1 1k v in 1v p-p c1 470pf Ca in 1809 ta01a +a in r3 49.9 frequency (mhz) 0.3 C70 distortion (db) C60 C50 C40 11030 1809 ta01b C80 C90 C100 C110 a v = +1 v in = 2v p-p v s = 5v r l = 100, 2nd r l = 1k, 3rd r l = 1k, 2nd r l = 100, 3rd
lt1809/lt1810 2 180910fa absolute maximum ratings total supply voltage (v + to v C ) ............................. 12.6v input voltage (note 2) ............................................... v s input current (note 2) ......................................... 10ma output short-circuit duration (note 3) ............ inde? nite operating temperature range (note 4) ...C 40c to 85c (note 1) out 1 v C 2 +in 3 6 v + 5 shdn 4 Cin top view s6 package 6-lead plastic tsot-23 t jmax = 150c, ja = 145c/w (note 9) 1 2 3 4 8 7 6 5 top view nc v + out nc shdn Cin +in v C s8 package 8-lead plastic so C + t jmax = 150c, ja = 100c/w (note 9) 1 2 3 4 out a Cin a +in a v C 8 7 6 5 v + out b Cin b +in b top view ms8 package 8-lead plastic msop t jmax = 150c, ja = 130c/w (note 9) top view v + out b Cin b +in b out a Cin a +in a v C s8 package 8-lead plastic so 1 2 3 4 8 7 6 5 a b t jmax = 150c, ja = 100c/w (note 9) pin configuration order information lead free finish tape and reel part marking package description specified temperature range lt1809cs6#pbf lt1809cs6#trpbf ltky 6-lead plastic tsot-23 0c to 70c lt1809is6#pbf lt1809is6#trpbf ltuf 6-lead plastic tsot-23 C40c to 85c lt1809cs8#pbf lt1809cs8#trpbf 1809 8-lead plastic so 0c to 70c lt1809is8#pbf lt1809is8#trpbf 1809i 8-lead plastic so C40c to 85c lt1810cms8#pbf lt1810cms8#trpbf ltrf 8-lead plastic msop 0c to 70c lt1810ims8#pbf lt1810ims8#trpbf lttq 8-lead plastic msop C40c to 85c lt1810cs8#pbf lt1810cs8#trpbf 1810 8-lead plastic so 0c to 70c lt1810is8#pbf lt1810is8#trpbf 1810i 8-lead plastic so C40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ speci? ed temperature range (note 5) ....C40c to 85c junction temperature ........................................... 150c storage temperature range .................. C65c to 150c lead temperature (soldering, 10 sec)................... 300c
lt1809/lt1810 3 180910fa electrical characteristics t a = 25c. v s = 5v, 0v; v s = 3v, 0v; v shdn = open; v cm = v out = half supply, unless otherwise noted. symbol parameter conditions min typ max units v os input offset voltage v cm = v + lt1809 so-8 v cm = v C lt1809 so-8 v cm = v + v cm = v C 0.6 0.6 0.6 0.6 2.5 2.5 3.0 3.0 mv mv mv mv v os input offset shift v cm = v C to v + lt1809 so-8 v cm = v C to v + 0.3 0.3 2.0 2.5 mv mv input offset voltage match (channel-to-channel) (note 10) 0.7 6 mv i b input bias current v cm = v + v cm = v C + 0.2v C27.5 1.8 C13 8a a i b input bias current shift v cm = v C + 0.2v to v + 14.8 35.5 a input bias current match (channel-to-channel) (note 10) v cm = v + v cm = v C + 0.2v 0.1 0.2 4 8 a a i os input offset current v cm = v + v cm = v C + 0.2v 0.05 0.2 1.2 4 a a i os input offset current shift v cm = v C + 0.2v to v + 0.25 5.2 a e n input noise voltage density f = 10khz 16 nv/ hz i n input noise current density f = 10khz 5 pa/ hz c in input capacitance 2pf a vol large-signal voltage gain v s = 5v, v o = 0.5v to 4.5v, r l = 1k to v s /2 v s = 5v, v o = 1v to 4v, r l = 100 to v s /2 v s = 3v, v o = 0.5v to 2.5v, r l = 1k to v s /2 25 4 15 80 10 42 v/mv v/mv v/mv cmrr common mode rejection ratio v s = 5v, v cm = v C to v + v s = 3v, v cm = v C to v + 66 61 82 78 db db cmrr match (channel-to-channel) (note 10) v s = 5v, v cm = v C to v + v s = 3v, v cm = v C to v + 60 55 82 78 db db input common mode range v C v + v psrr power supply rejection ratio v s = 2.5v to 10v, v cm = 0v 71 87 db psrr match (channel-to-channel) (note 10) v s = 2.5v to 10v, v cm = 0v 65 87 db minimum supply voltage (note 6) 2.3 2.5 v v ol output voltage swing low (note 7) no load i sink = 5ma i sink = 25ma 12 50 180 50 120 375 mv mv mv v oh output voltage swing high (note 7) no load i source = 5ma i source = 25ma 20 80 330 80 180 650 mv mv mv i sc short-circuit current v s = 5v v s = 3v 45 35 85 70 ma ma i s supply current per ampli? er 12.5 17 ma supply current, shutdown v s = 5v, v shdn = 0.3v v s = 3v, v shdn = 0.3v 0.55 0.31 1.25 0.90 ma ma i shdn shdn pin current v s = 5v, v shdn = 0.3v v s = 3v, v shdn = 0.3v 420 220 750 500 a a output leakage current, shutdown v shdn = 0.3v 0.1 75 a v l shdn pin input voltage low 0.3 v v h shdn pin input voltage high v s C 0.5 v t on turn-on time v shdn = 0.3v to 4.5v, r l = 100 80 ns
lt1809/lt1810 4 180910fa electrical characteristics t a = 25c. v s = 5v, 0v; v s = 3v, 0v; v shdn = open; v cm = v out = half supply, unless otherwise noted. symbol parameter conditions min typ max units t off turn-off time v shdn = 4.5v to 0.3v, r l = 100 50 ns gbw gain-bandwidth product frequency = 2mhz 160 mhz sr slew rate v s = 5v, a v = C1, r l = 1k, v o = 4v p-p 300 v/s fpbw full power bandwidth v s = 5v, v out = 4v p-p 23.5 mhz thd total harmonic distortion v s = 5v, a v = 1, r l = 1k, v o = 2v p-p , f c = 5mhz C 86 db t s settling time 0.1%, v s = 5v, v step = 2v, a v = C1, r l = 500 27 ns g differential gain (ntsc) v s = 5v, a v = 2, r l = 150 0.015 % ? differential phase (ntsc) v s = 5v, a v = 2, r l = 150 0.05 deg the l denotes the speci? cations which apply over the 0c t a 70c temperature range. v s = 5v, 0v; v s = 3v, 0v; v shdn = open; v cm = v out = half supply, unless otherwise noted. symbol parameter conditions min typ max units v os input offset voltage v cm = v + lt1809 so-8 v cm = v C lt1809 so-8 v cm = v + v cm = v C l l l l 1 1 1 1 3.0 3.0 3.5 3.5 mv mv mv mv v os tc input offset voltage drift (note 8) v cm = v + v cm = v C l l 9 9 25 25 v/c v/c v os input offset voltage shift v cm = v C to v + lt1809 so-8 v cm = v C to v + l l 0.5 0.5 2.5 3.0 mv mv input offset voltage match (channel-to-channel) (note 10) v cm = v C , v cm = v + l 1.2 6.5 mv i b input bias current v cm = v + C 0.2v v cm = v C + 0.4v l l C30 2 C14 10 a a i b input bias current shift v cm = v C + 0.4v to v + C 0.2v l 16 40 a input bias current match (channel-to-channel) (note 10) v cm = v + C 0.2v v cm = v C + 0.4v l 0.1 0.5 5 10 a a i os input offset current v cm = v + C 0.2v v cm = v C + 0.4v l l 0.05 0.40 1.5 4.5 a a i os input offset current shift v cm = v C + 0.4v to v + C 0.2v l 0.45 6 a a vol large-signal voltage gain v s = 5v, v o = 0.5v to 4.5v, r l = 1k to v s /2 v s = 5v, v o = 1v to 4v, r l = 100 to v s /2 v s = 3v, v o = 0.5v to 2.5v, r l = 1k to v s /2 l l l 20 3.5 12 75 8.5 40 v/mv v/mv v/mv cmrr common mode rejection ratio v s = 5v, v cm = v C to v + v s = 3v, v cm = v C to v + l l 64 60 80 75 db db cmrr match (channel-to-channel) (note 10) v s = 5v, v cm = v C , v cm = v + v s = 3v, v cm = v C , v cm = v + l 58 54 80 75 db db input common mode range l v C v + v psrr power supply rejection ratio v s = 2.5v to 10v, v cm = 0v l 70 83 db psrr match (channel-to-channel) (note 10) v s = 2.5v to 10v, v cm = 0v l 64 83 db minimum supply voltage (note 6) l 2.3 2.5 v v ol output voltage swing low (note 7) no load i sink = 5ma i sink = 25ma l l l 12 55 200 60 140 400 mv mv mv
lt1809/lt1810 5 180910fa electrical characteristics the l denotes the speci? cations which apply over the 0c t a 70c temperature range. v s = 5v, 0v; v s = 3v, 0v; v shdn = open; v cm = v out = half supply, unless otherwise noted. symbol parameter conditions min typ max units v oh output voltage swing high (note 7) no load i source = 5ma i source = 25ma l l l 50 110 370 120 220 700 mv mv mv i sc short-circuit current v s = 5v v s = 3v l l 40 30 75 65 ma ma i s supply current per ampli? er l 15 20 ma supply current, shutdown v s = 5v, v shdn = 0.3v v s = 3v, v shdn = 0.3v l l 0.58 0.35 1.4 1.1 ma ma i shdn shdn pin current v s = 5v, v shdn = 0.3v v s = 3v, v shdn = 0.3v l l 420 220 850 550 a a output leakage current, shutdown v shdn = 0.3v l 2a v l shdn pin input voltage low l 0.3 v v h shdn pin input voltage high l v s C 0.5 v t on turn-on time v shdn = 0.3v to 4.5v, r l = 100 l 80 ns t off turn-off time v shdn = 4.5v to 0.3v, r l = 100 l 50 ns gbw gain-bandwidth product frequency = 2mhz l 145 mhz sr slew rate v s = 5v, a v = C1, r l = 1k, v o = 4v p-p l 250 v/s fpbw full power bandwidth v s = 5v, v out = 4v p-p l 20 mhz symbol parameter conditions min typ max units v os input offset voltage v cm = v + lt1809 so-8 v cm = v C lt1809 so-8 v cm = v + v cm = v C l l l l 1 1 1 1 3.5 3.5 4.0 4.0 mv mv mv mv v os tc input offset voltage drift (note 8) v cm = v + v cm = v C l l 9 9 25 25 v/c v/c v os input offset voltage shift v cm = v C to v + lt1809 so-8 v cm = v C l l 0.5 0.5 3.0 3.5 mv mv input offset voltage match (channel-to-channel) (note 10) v cm = v + , v cm = v C l 1.2 7 mv i b input bias current v cm = v + C 0.2v v cm = v C + 0.4v l l C35 2 C17 12 a a i b input bias current shift v cm = v C + 0.4v to v + C 0.2v l 19 47 a input bias current match (channel-to-channel) (note 10) v cm = v + C 0.2v v cm = v C + 0.4v l l 0.2 0.6 6 12 a a i os input offset current v cm = v + C 0.2v v cm = v C + 0.4v l l 0.08 0.5 2 6 a a i os input offset current shift v cm = v C + 0.4v to v + C 0.2v l 0.58 7.5 a a vol large-signal voltage gain v s = 5v, v o = 0.5v to 4.5v, r l = 1k to v s /2 v s = 5v, v o = 1v to 4v, r l = 100 to v s /2 v s = 3v, v o = 0.5v to 2.5v, r l = 1k to v s /2 l l l 17 2.5 10 60 7 35 v/mv v/mv v/mv the l denotes the speci? cations which apply over the C 40c t a 85c temperature range. v s = 5v, 0v; v s = 3v, 0v; v shdn = open; v cm = v out = half supply, unless otherwise noted. (note 5)
lt1809/lt1810 6 180910fa electrical characteristics symbol parameter conditions min typ max units cmrr common mode rejection ratio v s = 5v, v cm = v C to v + v s = 3v, v cm = v C to v + l l 63 58 80 75 db db cmrr match (channel-to-channel) (note 10) v s = 5v, v cm = v C to v + v s = 3v, v cm = v C to v + l l 57 52 78 72 db db input common mode range l v C v + v psrr power supply rejection ratio v s = 2.5v to 10v, v cm = 0v l 69 83 db psrr match (channel-to-channel) (note 10) v s = 2.5v to 10v, v cm = 0v l 63 83 db minimum supply voltage (note 6) l 2.3 2.5 v v ol output voltage swing low (note 7) no load i sink = 5ma i sink = 25ma l l l 18 60 210 70 150 450 mv mv mv v oh output voltage swing high (note 7) no load i source = 5ma i source = 25ma l l l 55 120 375 130 240 750 mv mv mv i sc short-circuit current v s = 5v v s = 3v l l 30 25 70 60 ma ma i s supply current per ampli? er l 15 21 ma supply current, shutdown v s = 5v, v shdn = 0.3v v s = 3v, v shdn = 0.3v l l 0.58 0.35 1.5 1.2 ma ma i shdn shdn pin current v s = 5v, v shdn = 0.3v v s = 3v, v shdn = 0.3v 420 220 900 600 a a output leakage current, shutdown v shdn = 0.3v 3a v l shdn pin input voltage low 0.3 v v h shdn pin input voltage high v s C 0.5 v t on turn-on time v shdn = 0.3v to 4.5v, r l = 100 80 ns t off turn-off time v shdn = 4.5v to 0.3v, r l = 100 50 ns gbw gain-bandwidth product frequency = 2mhz 140 mhz sr slew rate v s = 5v, a v = -1, r l = 1k, v o = 4v p-p 180 v/s fpbw full power bandwidth v s = 5v, v out = 4v p-p 14 mhz the l denotes the speci? cations which apply over the C 40c t a 85c temperature range. v s = 5v, 0v; v s = 3v, 0v; v shdn = open; v cm = v out = half supply, unless otherwise noted. (note 5) t a = 25c. v s = 5v, v shdn = open, v cm = 0v, v out = 0v, unless otherwise noted. symbol parameter conditions min typ max units v os input offset voltage v cm = v + lt1809 so-8 v cm = v C lt1809 so-8 v cm = v + v cm = v C 0.8 0.8 0.8 0.8 3.0 3.0 3.5 3.5 mv mv mv mv v os input offset voltage shift v cm = v C to v + lt1809 so-8 v cm = v C to v + 0.35 0.35 2.5 3.0 mv mv input offset voltage match (channel-to-channel) (note 10) v cm = v + , v cm = v C 16 mv i b input bias current v cm = v + v cm = v C + 0.2v C30 2 C12.5 10 a a
lt1809/lt1810 7 180910fa t a = 25c. v s = 5v, v shdn = open, v cm = 0v, v out = 0v, unless otherwise noted. electrical characteristics symbol parameter conditions min typ max units i b input bias current shift v cm = v C + 0.2v to v + 14.5 40 a input bias current match (channel-to-channel) (note 10) v cm = v + v cm = v C + 0.2v 0.1 0.4 5 10 a a i os input offset current v cm = v + v cm = v C + 0.2v 0.05 0.40 2 5 a a i os input offset current shift v cm = v C + 0.2v to v + 0.45 7 a e n input noise voltage density f = 10khz 16 nv/ hz i n input noise current density f = 10khz 5 pa/ hz c in input capacitance f = 100khz 2 pf a vol large-signal voltage gain v o = C4v to 4v, r l = 1k v o = C2.5v to 2.5v, r l = 100 30 4.5 100 12 v/mv v/mv cmrr common mode rejection ratio v cm = v C to v + 70 89 db cmrr match (channel-to-channel) (note 10) v cm = v C to v + 64 89 db input common mode range v C v + v psrr power supply rejection ratio v + = 2.5v to 10v, v C = 0v 71 87 db psrr match (channel-to-channel) (note 10) v + = 2.5v to 10v, v C = 0v 65 90 db v ol output voltage swing low (note 7) no load i sink = 5ma i sink = 25ma 12 50 180 60 140 425 mv mv mv v oh output voltage swing high (note 7) no load i source = 5ma i source = 25ma 35 90 310 100 200 700 mv mv mv i sc short-circuit current 55 85 ma i s supply current per ampli? er 15 20 ma supply current, shutdown v shdn = 0.3v 0.6 1.3 ma i shdn shdn pin current v shdn = 0.3v 420 750 a output leakage current, shutdown v shdn = 0.3v 0.1 75 a v l shdn pin input voltage low 0.3 v v h shdn pin input voltage high v + C 0.5 v t on turn-on time v shdn = 0.3v to 4.5v, r l = 100 80 ns t off turn-off time v shdn = 4.5v to 0.3v, r l = 100 50 ns gbw gain-bandwidth product frequency = 2mhz 110 180 mhz sr slew rate a v = C1, r l = 1k, v o = 4v, measured at v o = 3v 175 350 v/s fpbw full power bandwidth v out = 8v p-p 14 mhz thd total harmonic distortion a v = 1, r l = 1k, v o = 2v p-p , f c = 5mhz C90 db t s settling time 0.1%, v step = 8v, a v = C1, r l = 500 34 ns g differential gain (ntsc) a v = 2, r l = 150 0.01 % ? differential phase (ntsc) a v = 2, r l = 150 0.01 deg
lt1809/lt1810 8 180910fa the denotes the speci? cations which apply over the 0c t a 70c temperature range. v s = 5v, v shdn = open, v cm = 0v, v out = 0v, unless otherwise noted. electrical characteristics symbol parameter conditions min typ max units v os input offset voltage v cm = v + lt1809 so-8 v cm = v C lt1809 so-8 v cm = v + v cm = v C l l l l 1 1 1 1 3.25 3.25 3.75 3.75 mv mv mv mv v os tc input offset voltage drift (note 8) v cm = v + v cm = v C l l 10 10 25 25 v/c v/c v os input offset voltage shift v cm = v C to v + lt1809 so-8 v cm = v C to v + l l 0.5 0.5 2.75 3.25 mv mv input offset voltage match (channel-to-channel) (note 10) v cm = v C to v + l 1.2 6.5 mv i b input bias current v cm = v + C 0.2v l 2.5 12.5 a v cm = v C + 0.4v l C37.5 C15 a i b input bias current shift v cm = v C + 0.4v to v + C 0.2v l 17.5 50 a input bias current match (channel-to-channel) (note 10) v cm = v + C 0.2v v cm = v C + 0.4v l l 0.1 0.5 6 12 a a i os input offset current v cm = v + C 0.2v v cm = v C + 0.4v l l 0.06 0.5 2.25 6 a a i os input offset current shift v cm = v C + 0.4v to v + C 0.2v l 0.56 8.25 a a vol large-signal voltage gain v o = C4v to 4v, r l = 1k v o = C2.5v to 2.5v, r l = 100 l l 27 3.5 80 10 v/mv v/mv cmrr common mode rejection ratio v cm = v C to v + l 69 86 db cmrr match (channel-to-channel) (note 10) v cm = v C to v + l 63 86 db input common mode range l v C v + v psrr power supply rejection ratio v + = 2.5v to 10v, v C = 0v l 70 83 db psrr match (channel-to-channel) (note 10) v + = 2.5v to 10v, v C = 0v l 64 83 db v ol output voltage swing low (note 7) no load i sink = 5ma i sink = 25ma l l l 20 50 210 80 160 475 mv mv mv v oh output voltage swing high (note 7) no load i source = 5ma i source = 25ma l l l 60 120 370 140 240 750 mv mv mv i sc short-circuit current l 45 75 ma i s supply current per ampli? er l 17.5 25 ma supply current, shutdown v shdn = 0.3v l 0.6 1.5 ma i shdn shdn pin current v shdn = 0.3v l 420 850 a output leakage current, shutdown v shdn = 0.3v l 3a v l shdn pin input voltage low l 0.3 v v h shdn pin input voltage high l v + C 0.5 v t on turn-on time v shdn = 0.3v to 4.5v, r l = 100 l 80 ns t off turn-off time v shdn = 4.5v to 0.3v, r l = 100 l 50 ns gbw gain-bandwidth product frequency = 2mhz l 85 170 mhz sr slew rate a v = C1, r l = 1k, v o = 4v, measured at v o = 3v l 140 300 v/s fpbw full power bandwidth v out = 8v p-p l 12 mhz
lt1809/lt1810 9 180910fa the denotes the speci? cations which apply over the C 40c t a 85c temperature range. v s = 5v, v shdn = open, v cm = 0v, v out = 0v, unless otherwise noted. (note 5) electrical characteristics symbol parameter conditions min typ max units v os input offset voltage v cm = v + lt1809 so-8 v cm = v C lt1809 so-8 v cm = v + v cm = v Cv l l l l 1 1 1 1 3.75 3.75 4.25 4.25 mv mv mv mv v os tc input offset voltage drift (note 8) v cm = v + v cm = v C l l 10 10 25 25 v/c v/c v os input offset voltage shift v cm = v C to v + lt1809 so-8 v cm = v C to v + l l 0.5 0.5 3.00 3.75 mv mv input offset voltage match (channel-to-channel) (note 10) v cm = v C to v + l 1.2 7.5 mv i b input bias current v cm = v + C 0.2v v cm = v C + 0.4v l l C45 2.8 C17 14 a a i b input bias current shift v cm = v C + 0.4v to v + C 0.2v l 19.8 59 a input bias current match (channel-to-channel) (note 10) v cm = v + C 0.2v v cm = v C + 0.4v l l 0.1 0.6 7 14 a a i os input offset current v cm = v + C 0.2v v cm = v C + 0.4v l l 0.08 0.6 2.5 8 a a i os input offset current shift v cm = v C + 0.4v to v + C 0.2v l 0.68 10.5 a a vol large-signal voltage gain v o = C4v to 4v, r l = 1k v o = C2.5v to 2.5v, r l = 100 l l 22 3 70 10 v/mv v/mv cmrr common mode rejection ratio v cm = v C to v + l 68 86 db cmrr match (channel-to-channel) (note 10) v cm = v C to v + l 62 86 db input common mode range l v C v + v psrr power supply rejection ratio v + = 2.5v to 10v, v C = 0v l 69 83 db psrr match (channel-to-channel) (note 10) v + = 2.5v to 10v, v C = 0v l 63 83 db v ol output voltage swing low (note 7) no load i sink = 5ma i sink = 25ma l l l 23 60 220 100 170 525 mv mv mv v oh output voltage swing high (note 7) no load i source = 5ma i source = 25ma l l l 75 130 375 160 260 775 mv mv mv i sc short-circuit current l 30 75 ma i s supply current per ampli? er l 19 25 ma supply current, shutdown v shdn = 0.3v l 0.65 1.6 ma i shdn shdn pin current v shdn = 0.3v l 420 900 a output leakage current, shutdown v shdn = 0.3v l 4a v l shdn pin input voltage low l 0.3 v v h shdn pin input voltage high l v + C 0.5 v t on turn-on time v shdn = 0.3v to 4.5v, r l = 100 l 80 ns t off turn-off time v shdn = 4.5v to 0.3v, r l = 100 l 50 ns gbw gain-bandwidth product frequency = 2mhz l 80 160 mhz sr slew rate a v = C1, r l = 1k, v o = 4v, measured at v o = 3v l l 110 220 v/s fpbw full power bandwidth v out = 8v p-p l 8.5 mhz
lt1809/lt1810 10 180910fa note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the inputs are protected by back-to-back diodes. if the differential input voltage exceeds 1.4v, the input current should be limited to less than 10ma. note 3: a heat sink may be required to keep the junction temperature below the absolute maximum rating when the output is shorted inde? nitely. note 4: the lt1809c/lt1809i and lt1810c/lt1810i are guaranteed functional over the operating temperature range of C 40c and 85c. note 5: the lt1809c/lt1810c are guaranteed to meet speci? ed performance from 0c to 70c. the lt1809c/lt1810c are designed, characterized and expected to meet speci? ed performance from C40c to 85c but are not tested or qa sampled at these temperatures. the lt1809i/lt1810i are guaranteed to meet speci? ed performance from C40c to 85c. note 6: minimum supply voltage is guaranteed by power supply rejection ratio test. note 7: output voltage swings are measured between the output and power supply rails. note 8: this parameter is not 100% tested. note 9: thermal resistance varies depending upon the amount of pc board metal attached to the v C pin of the device. ja is speci? ed for a certain amount of 2oz of copper metal trace connecting to the v C pin as described in the thermal resistance tables in the applications information section. note 10: matching parameters are the difference between the two ampli? ers of the lt1810. electrical characteristics
lt1809/lt1810 11 180910fa typical performance characteristics supply current vs supply voltage offset voltage vs input common mode input bias current vs common mode voltage input bias current vs temperature output saturation voltage vs load current (output low) output saturation voltage vs load current (output high) v os distribution, v cm = 0v (pnp stage) v os distribution, v cm = 5v (npn stage) v os shift for v cm = 0v to 5v input offset voltage (mv) C3 0 percent of units (%) 10 20 30 40 50 C2 C1 0 1 1809 g01 23 v s = 5v, 0v input offset voltage (mv) C3 0 percent of units (%) 10 20 30 40 50 C2 C1 0 1 1809 g02 23 v s = 5v, 0v input offset voltage (mv) C1 0 percent of units (%) 5 10 15 20 25 C0.75 C0.5 C0.25 0 0.25 1809 g03 0.5 0.75 1 v s = 5v, 0v total supply voltage (v) 0 supply current (ma) 15 20 25 8 1809 g04 10 5 0 2 4 6 19 3 5 7 10 t a = 125c t a = 25c t a = C55c input common mode voltage (v) 0 1.0 1.5 2.0 4 1809 g05 0.5 0 123 5 C0.5 C1.0 C1.5 offset voltage (mv) v s = 5v, 0v typical part t a = 125c t a = 25c t a = C55c common mode voltage (v) C1 input bias current (a) 5 2 1809 g06 C10 C20 01 3 C25 C30 10 0 C5 C15 456 v s = 5v, 0v t a = C55c t a = C55c t a = 25c t a = 25c t a = 125c t a = 125c temperature (c) C50 C15 input bias current (a) C13 C9 C7 C5 5 C1 C20 10 25 85 1809 g07 C11 1 3 C3 C35 C5 40 55 70 v s = 5v, 0v v cm = 5v v cm = 0v load current (ma) 0.01 0.001 output low saturation voltage (v) 0.1 10 110 0.1 100 1809 g08 0.01 1 v s = 5v, 0v t a = 125c t a = C55c t a = 25c load current (ma) 0.01 0.001 output high saturation voltage (v) 0.1 10 110 0.1 100 1809 g09 0.01 1 v s = 5v, 0v t a = 125c t a = C55c t a = 25c
lt1809/lt1810 12 180910fa typical performance characteristics shdn pin current vs shdn pin voltage open-loop gain open-loop gain open-loop gain offset voltage vs output current warm-up drift vs time (lt1809s8) minimum supply voltage output short-circuit current vs power supply voltage supply current vs shdn pin voltage total supply voltage (v) 1.5 C1.0 change in offset voltage (mv) C0.8 C0.4 C0.2 0 1.0 0.4 2.5 3.5 4.0 1809 g10 C0.6 0.6 0.8 0.2 2.0 3.0 4.5 5.0 t a = 125c t a = C55c v cm = vC + 0.5v t a = 25c power supply voltage (v) 1.5 output short-circuit current (ma) C40 80 100 120 2.5 3.5 4.0 1809 g11 C80 40 0 C60 60 C100 20 C20 2.0 3.0 4.5 5.0 t a = C55c t a = C55c t a = 125c t a = 25c sinking sourcing t a = 25c t a = 125c shdn pin voltage (v) 0 0 supply current (ma) 2 6 8 10 2 4 5 18 1809 g12 4 13 12 14 16 v s = 5v, 0v t a = C55c t a = 25c t a = 125c shdn pin voltage (v) 0 shdn pin current (a) C150 C50 50 4 1809 g13 C250 C350 C200 C100 0 C300 C400 C450 1 2 3 5 v s = 5v, 0v t a = 125c t a = 25c t a = C55c output voltage (v) 0 C2.5 input voltage (mv) C1.5 C0.5 0.5 0.5 1.0 1.5 2.0 1809 g14 2.5 1.5 2.5 C2.0 C1.0 0 1.0 2.0 3.0 r l = 100 v s = 3v, 0v r l = 1k output voltage (v) 0 C2.5 input voltage (mv) C1.5 C0.5 0.5 1 2 34 1809 g15 1.5 2.5 C2.0 C1.0 0 1.0 2.0 5 r l = 100 v s = 5v, 0v r l = 1k output voltage (v) C5 input voltage (mv) 0.5 1.5 2.5 3 1809 g16 C0.5 C1.5 0 1.0 2.0 C1.0 C2.0 C2.5 C3 C4 C1 C2 12 4 0 5 v s = 5v r l = 1k r l = 100 output current (ma) C15 offset voltage (mv) C5 5 15 C10 0 10 C60 C20 20 60 1809 g17 100 C80 C100 C40 0 40 80 v s = 5v t a = 125c t a = C55c t a = 25c time after power up (sec) 0 change in offset voltage (v) 100 120 140 80 100 120 140 160 1809 g18 80 60 0 20 40 60 20 40 180 160 t a = 25c v s = 5v v s = 5v, 0v v s = 3v, 0v
lt1809/lt1810 13 180910fa typical performance characteristics gain bandwidth and phase margin vs supply voltage gain bandwidth and phase margin vs temperature slew rate vs temperature gain and phase vs frequency closed-loop gain vs frequency closed-loop gain vs frequency input noise voltage vs frequency input noise current vs frequency 0.1hz to 10hz output voltage noise frequency (khz) 0.1 40 noise voltage (nv/ hz ) 50 60 70 80 1 10 100 1809 g19 30 20 10 0 90 100 v s = 5v, 0v npn active v cm = 4.5v pnp active v cm = 2.5v frequency (khz) 0.1 0 current noise (pa/ hz ) 12 16 20 1 10 100 1809 g20 8 4 v s = 5v, 0v pnp active v cm = 2.5v npn active v cm = 4.5v time (2s/div) output voltage (v/div) 2 6 10 1809 g21 C2 C6 0 4 8 C4 C8 C10 total supply voltage (v) 0 gain bandwidth (mhz) phase margin (deg) 190 8 1809 g22 180 170 185 175 165 160 35 45 55 40 50 2 4 6 10 t a = 25c r l = 1k phase margin gain bandwidth temperature (c) C55 150 gain bandwidth (mhz) phase margin (deg) 160 180 190 200 0 50 75 1809 g23 170 30 55 40 45 50 35 C25 25 100 125 v s = 5v v s = 5v v s = 3v, 0v v s = 3v, 0v gain bandwidth phase margin temperature (c) C55 slew rate (v/s) 400 25 1809 g24 250 150 C25 0 50 100 50 450 350 300 200 75 100 125 a v = 1 r f = r g = 1k r l = 1k rising and falling slew rate v s = 5v v s = 5v, 0v frequency (hz) 0 gain (db) phase (deg) 20 30 50 60 100k 10m 100m 1g 1809 g25 C20 1m 40 10 C10 C20 20 40 80 100 C60 60 0 C40 v s = 5v v s = 5v v s = 3v, 0v phase gain v s = 3v, 0v c l = 5pf r l = 1k frequency (hz) C6 gain (db) 12 15 C9 C12 9 0 6 3 C3 100k 10m 100m 500m 1809 g26 C15 1m v s = 3v a v = +1 v s = 5v frequency (hz) C6 gain (db) 12 15 C9 C12 9 0 6 3 C3 100k 10m 100m 500m 1809 g27 C15 1m v s = 3v a v = +2 v s = 5v
lt1809/lt1810 14 180910fa typical performance characteristics series output resistor vs capacitive load series output resistor vs capacitive load 0.01% settling time distortion vs frequency distortion vs frequency distortion vs frequency output impedance vs frequency common mode rejection ratio vs frequency power supply rejection ratio vs frequency frequency (hz) 100k 1m 10m 100m 500m 0.01 output impedance () 1 600 1809 g28 0.1 10 100 v s = 5v, 0v a v = 10 a v = 1 a v = 2 frequency (hz) 10k 50 common mode rejection ratio (db) 60 70 80 90 100k 1m 10m 100m 500m 1809 g29 40 30 20 10 100 110 v s = 5v, 0v frequency (hz) 1k 10k 40 power supply rejection ratio (db) 50 60 70 80 100k 1m 10m 100m 1809 g30 30 20 10 0 90 100 v s = 5v, 0v t a = 25c positive supply negative supply capacitive load (pf) 10 0 overshoot (%) 10 20 40 100 1000 1809 g31 30 5 15 35 25 v s = 5v, 0v a v = +1 r s = 10, r l = r s = 20, r l = r l = r s = 50 capacitive load (pf) 10 0 overshoot (%) 10 20 30 40 100 1000 1809 g32 50 5 15 25 35 45 v s = 5v, 0v a v = +2 r s = 10 r l = r s = 20 r l = r l = r s = 50 20ns/div) 1809 g33 input signal generation (2v/div) v s = 5v v out = 4v a v = C1 r l = 500 t s = 110ns (settling time) output settling resolution (2mv/div) frequency (mhz) 0.3 C70 distortion (db) C60 C50 C40 11030 1809 g34 C80 C90 C100 C110 a v = +1 v o = 2v p-p v s = 5v r l = 100, 2nd r l = 1k, 3rd r l = 1k, 2nd r l = 100, 3rd frequency (mhz) 0.3 C70 distortion (db) C60 C50 C40 11030 1809 g35 C80 C90 C100 C110 a v = +1 v o = 2v p-p v s = 5v r l = 100, 2nd r l = 1k, 3rd r l = 1k, 2nd r l = 100, 3rd frequency (mhz) 0.3 C70 distortion (db) C60 C50 C40 11030 1809 g36 C80 C90 C100 C110 a v = +2 v o = 2v p-p v s = 5v r l = 100, 2nd r l = 100, 3rd r l = 1k, 3rd r l = 1k, 2nd
lt1809/lt1810 15 180910fa typical performance characteristics 5v large-signal response 5v small-signal response 5v large-signal response 5v small-signal response output overdriven recovery shutdown response distortion vs frequency maximum undistorted output signal vs frequency frequency (mhz) 0.3 C70 distortion (db) C60 C50 C40 11030 1809 g37 C80 C90 C100 C110 a v = +2 v o = 2v p-p v s = 5v r l = 100, 2nd r l = 100, 3rd r l = 1k, 3rd r l = 1k, 2nd frequency (mhz) 0.1 4.3 output voltage swing (v p-p ) 4.4 4.5 4.6 1 10 100 1809 g38 4.2 4.1 4.0 3.9 v s = 5v a v = C1 a v = +2 10ns/div) 1809 g39 v s = 5v a v = +1 r l = 1k 10ns/div) 1809 g40 v s = 5v a v = +1 r l = 1k 10ns/div) 1809 g41 v s = 5v a v = +1 r l = 1k 10ns/div) 1809 g42 v s = 5v a v = +1 r l = 1k 10ns/div) 1809 g43 v s = 5v, 0v a v = +2 v in (1v/div) v out (2v/div) 0v) 0v) 100ns/div) 1809 g44 v s = 5v, 0v a v = +2 r l = 100 v shdn v out 0v) 0v)
lt1809/lt1810 16 180910fa applications information rail-to-rail characteristics the lt1809/lt1810 have an input and output signal range that includes both negative and positive power supply. figure 1 depicts a simpli? ed schematic of the ampli? er. the input stage is comprised of two differential ampli? ers, a pnp stage q1/q2 and a npn stage q3/q4 that are active over different ranges of common mode input voltage. the pnp differential pair is active for common mode voltages between the negative supply to approximately 1.5v below the positive supply. as the input voltage moves closer toward the positive supply, the transistor q5 will steer the tail current i 1 to the current mirror q6/q7, activating the npn differential pair and causing the pnp pair to become inactive for the rest of the input common mode range up to the positive supply. a pair of complementary common emitter stages q14/q15 form the output stage, enabling the output to swing from rail-to-rail. the capacitors c1 and c2 form the local feedback loops that lower the output impedance at high frequency. these devices are fabricated on linear technologys proprietary high speed complementary bipolar process. power dissipation the lt1809/lt1810 ampli? ers combine high speed with large output current in a small package, so there is a need to ensure that the dies junction temperature does not exceed 150c. the lt1809 is housed in an so-8 package or a 6-lead sot-23 package and the lt1810 is in an so-8 or 8-lead msop package. all packages have the v C sup- ply pin fused to the lead frame to enhance the thermal conductance when connecting to a ground plane or a large metal trace. metal trace and plated through-holes can be used to spread the heat generated by the device to the backside of the pc board. for example, on a 3/32" fr-4 board with 2oz copper, a total of 660 square millimeters connected to pin 4 of lt1810 in an so-8 package (330 square millimeters on each side of the pc board) will bring the thermal resistance, ja , to about 85c/w. without extra metal trace connected to the v C pin to provide a heat sink, the thermal resistance will be around 105c/w. more information on thermal resistance for all packages with various metal areas connecting to the v C pin is provided in tables 1, 2 and 3 for thermal consideration. figure 1. lt1809 simpli? ed schematic diagram q4 q6 q3 q7 q10 q1 q13 q15 out q2 q11 q12 q9 q5 v bias i 1 d2 d1 d5 d4 d3 d6 d7 d8 esdd2 esdd1 +in Cin esdd3 esdd4 v + v + q8 r2 r1 r3 r4 r5 q14 1809 f01 i 2 c2 c c v C c1 buffer and output bias q17 q16 esdd5 shdn v + r7 100k r6 10k d9 v + v C v C v C v C esdd6 bias generation
lt1809/lt1810 17 180910fa applications information table 1. lt1809 6-lead sot-23 package copper area topside (mm 2 ) board area (mm 2 ) thermal resistance (junction-to-ambient) 270 2500 135c/w 100 2500 145c/w 20 2500 160c/w 0 2500 200c/w device is mounted on topside. table 2. lt1809/lt1810 so-8 package copper area topside (mm 2 ) backside (mm 2 ) board area (mm 2 ) thermal resistance (junction-to-ambient) 1100 1100 2500 65c/w 330 330 2500 85c/w 35 35 2500 95c/w 35 0 2500 100c/w 0 0 2500 105c/w device is mounted on topside. table 3. lt1810 8-lead msop package copper area topside (mm 2 ) backside (mm 2 ) board area (mm 2 ) thermal resistance (junction-to-ambient) 540 540 2500 110c/w 100 100 2500 120c/w 100 0 2500 130c/w 30 0 2500 135c/w 0 0 2500 140c/w device is mounted on topside. junction temperature t j is calculated from the ambient temperature t a and power dissipation p d as follows: t j = t a + (p d ? ja ) the power dissipation in the ic is the function of the supply voltage, output voltage and the load resistance. for a given supply voltage, the worst-case power dis- sipation p d(max) occurs at the maximum supply current with the output voltage at half of either supply voltage (or the maximum swing is less than 1/2 the supply voltage). p d(max) is given by: p d(max) = (v s ? i s(max) ) + (v s /2) 2 /r l example: an lt1810 in so-8 mounted on a 2500mm 2 area of pc board without any extra heat spreading plane con- nected to its v C pin has a thermal resistance of 105c/w, ja . operating on 5v supplies with both ampli? ers simultaneously driving 50 loads, the worst-case power dissipation is given by: p d(max) = 2 ? (10 ? 25ma) + 2 ? (2.5) 2 /50 = 0.5 + 0.250 = 0.750w the maximum ambient temperature that the part is al- lowed to operate is: t a = t j C (p d(max) ? 105c/w) = 150c C (0.750w ? 105c/w) = 71c to operate the device at higher ambient temperature, con- nect more metal area to the v C pin to reduce the thermal resistance of the package as indicated in table 2. input offset voltage the offset voltage will change depending upon which input stage is active and the maximum offset voltage is guaranteed to be less than 3mv. the change of v os over the entire input common mode range (cmrr) is less than 2.5mv on a single 5v and 3v supply. input bias current the input bias current polarity depends upon a given input common voltage at whichever input stage is operating. when the pnp input stage is active, the input bias cur- rents ? ow out of the input pins and ? ow into the input pins when the npn input stage is activated. because the input offset current is less than the input bias current, matching the source resistances at the input pin will reduce total offset error. output the lt1809/lt1810 can deliver a large output current, so the short-circuit current limit is set around 90ma to prevent damage to the device. attention must be paid to keep the junction temperature of the ic below the absolute maximum rating of 150c (refer to the power dissipation section) when the output is continuously short-circuited.
lt1809/lt1810 18 180910fa applications information the output of the ampli? er has reverse-biased diodes connected to each supply. if the output is forced beyond either supply, unlimited current will ? ow through these diodes. if the current is transient and limited to several hundred milliamps, no damage to the device will occur. overdrive protection when the input voltage exceeds the power supplies, two pairs of crossing diodes, d1 to d4, will prevent the out- put from reversing polarity. if the input voltage exceeds either power supply by 700mv, diodes d1/d2 or d3/d4 will turn on, keeping the output at the proper polarity. for the phase reversal protection to perform properly, the input current must be limited to less than 5ma. if the ampli? er is severely overdriven, an external resistor should be used to limit the overdrive current. the lt1809/lt1810s input stages are also protected against differential input voltages of 1.4v or higher by back-to-back diodes, d5/d8, that prevent the emitter- base breakdown of the input transistors. the current in these diodes should be limited to less than 10ma when they are active. the worst-case differential input voltage usually occurs when the input is driven while the output is shorted to ground in a unity-gain con? guration. in ad- dition, the ampli? er is protected against esd strikes up to 3kv on all pins by a pair of protection diodes on each pin that are connected to the power supplies as shown in figure 1. capacitive load the lt1809/lt1810 is optimized for high bandwidth and low distortion applications. it can drive a capacitive load about 20pf in a unity-gain con? guration and more with higher gain. when driving a larger capacitive load, a resistor of 10 to 50 should be connected between the output and the capacitive load to avoid ringing or oscillation. the feedback should still be taken from the output so that the resistor will isolate the capacitive load to ensure stability. graphs on capacitive loads indicate the transient response of the ampli? er when driving capacitive load with a speci- ? ed series resistor. feedback components when feedback resistors are used to set up gain, care must be taken to ensure that the pole formed by the feedback resistors and the total capacitance at the inverting input does not degrade stability. for instance, the lt1809 in a noninverting gain of 2, set up with two 1k resistors and a capacitance of 3pf (device plus pc board), will probably ring in transient response. the pole that is formed at 106mhz will reduce phase margin by 34 degrees when the crossover frequency of the ampli? er is around 70mhz. a capacitor of 3pf or higher connected across the feedback resistor will eliminate any ringing or oscillation. shdn pin the lt1809 has a shdn pin to reduce the supply current to less than 1.25ma. when the shdn pin is pulled low, it will generate a signal to power down the device. if the pin is left unconnected, an internal pull-up resistor of 10k will keep the part fully operating as shown in figure 1. the output will be high impedance during shutdown, and the turn-on and turn-off time is less than 100ns. because the inputs are protected by a pair of back-to-back diodes, the input signal will feed through to the output during shut- down mode if the amplitude of signal between the inputs is larger than 1.4v.
lt1809/lt1810 19 180910fa typical applications driving a/d converters the lt1809/lt1810 have a 27ns settling time to 0.1% of a 2v step signal and 20 output impedance at 100mhz making it ideal for driving high speed a/d converters. with the rail-to-rail input and output and low supply voltage operation, the lt1809 is also desirable for single supply applications. as shown in figure 2, the lt1809 drives a 10msps, 12-bit adc, the ltc1420. the lowpass ? lter, r3 and c1, reduces the noise and distortion products that might come from the input signal. high quality capacitors and resistors, an npo chip capacitor and metal-? lm surface mount resistors, should be used since these components can add to distortion. the voltage glitch of the converter, due to its sampling nature, is buffered by the lt1809 and the ability of the ampli? er to settle it quickly will affect the spurious-free dynamic range of the system. figure 2 to figure 7 depict the lt1809 driving the ltc1420 at different con? gurations and voltage supplies. the fft responses show better than 90db of sfdr for a 5v supply, and 80db on a 5v single supply for the 1.394mhz signal. figure 2. noninverting a/d driver figure 3. 4096 point fft response C + lt1809 ltc1420 pga gain = 1 ref = 2.048v 5v 5v 12 bits 10msps C5v C5v ? ? ? r2 1k r1 1k v in 1v p-p c1 470pf Ca in 1809 f02 +a in r3 49.9 frequency (mhz) 0 C120 amplitude (db) C100 C80 C60 C40 C20 0 1234 1809 f03 5 v s = 5v a v = +2 f sample = 10msps f in = 1.394mhz sfdr = 90db figure 4. inverting a/d driver figure 5. 4096 point fft response C + lt1809 ltc1420 pga gain = 1 ref = 2.048v 5v 5v 12 bits 10msps C5v C5v ? ? ? 1k 1k v in 2v p-p 470pf Ca in 1809 f04 +a in 49.9 frequency (mhz) 0 C120 amplitude (db) C100 C80 C60 C40 C20 0 1234 1809 f05 5 v s = 5v a v = C1 f sample = 10msps f in = 1.394mhz sfdr = 90db
lt1809/lt1810 20 180910fa typical applications figure 6. single supply a/d driver figure 7. 4096 point fft response C + lt1809 ltc1420 pga gain = 2 ref = 4.096v 5v 3 2 4 1 6 7 5v 12 bits 10msps ? ? ? 1k 1k v in 1v p-p on 2.5v dc 470pf 1f 0.15f 3 2 1 Ca in v cm 1809 f06 +a in 49.9 frequency (mhz) 0 C120 amplitude (db) C100 C80 C60 C40 C20 0 1234 1809 f07 5 v s = 5v a v = +2 f sample = 10msps f in = 1.394mhz sfdr = 80db single supply video line driver the lt1809 is a wideband rail-to-rail op amp with a large output current that allows it to drive video signals in low supply applications. figure 8 depicts a single supply video line driver with ac coupling to minimize the qui- escent power dissipation. resistors r1 and r2 are used to level-shift the input and output to provide the largest signal swing. a gain of 2 is set up with r3 and r4 to re- store the signal at v out , which is attenuated by 6db due to the matching of the 75 line with the back-terminated resistor, r5. the back termination will eliminate any re- ? ection of the signal that comes from the load. the input termination resistor, r t , is optionalit is used only if matching of the incoming line is necessary. the values of c1, c2 and c3 are selected to minimize the droop of the luminance signal. in some less stringent requirements, the value of capacitors could be reduced. the C 3db bandwidth of the driver is about 95mhz on 5v supply and the amount of peaking will vary upon the value of capacitor c4. figure 8. 5v single supply video line driver figure 9. video line driver frequency response C + lt1809 v in 1809 f08 c1 33f c2 150f r t 75 r load 75 v out r2 5k r3 1k r4 1k c4 3pf r1 5k 5v 2 3 6 7 4 r5 75 75 coax cable c3 1000f + + + frequency (mhz) C2 voltage gain (db) 4 5 C3 C4 3 0 2 1 C1 0.2 10 100 1809 f09 C5 1 v s = 5v
lt1809/lt1810 21 180910fa package description ms8 package 8-lead plastic msop (reference ltc dwg # 05-08-1660 rev f) msop (ms8) 0307 rev f 0.53 0.152 (.021 .006) seating plane note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.18 (.007) 0.254 (.010) 1.10 (.043) max 0.22 ?0.38 (.009 ?.015) typ 0.1016 0.0508 (.004 .002) 0.86 (.034) ref 0.65 (.0256) bsc 0 ?6 typ detail ? detail ? gauge plane 12 3 4 4.90 0.152 (.193 .006) 8 7 6 5 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) 0.52 (.0205) ref 5.23 (.206) min 3.20 ?3.45 (.126 ?.136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.42 0.038 (.0165 .0015) typ 0.65 (.0256) bsc
lt1809/lt1810 22 180910fa package description s6 package 6-lead plastic tsot-23 (reference ltc dwg # 05-08-1636 rev b) 1.50 ?1.75 (note 4) 2.80 bsc 0.30 ?0.45 6 plcs (note 3) datum ? 0.09 ?0.20 (note 3) s6 tsot-23 0302 rev b 2.90 bsc (note 4) 0.95 bsc 1.90 bsc 0.80 ?0.90 1.00 max 0.01 ?0.10 0.20 bsc 0.30 ?0.50 ref pin one id note: 1. dimensions are in millimeters 2. drawing not to scale 3. dimensions are inclusive of plating 4. dimensions are exclusive of mold flash and metal burr 5. mold flash shall not exceed 0.254mm 6. jedec package reference is mo-193 3.85 max 0.62 max 0.95 ref recommended solder pad layout per ipc calculator 1.4 min 2.62 ref 1.22 ref
lt1809/lt1810 23 180910fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description .016 ?.050 (0.406 ?1.270) .010 ?.020 (0.254 ?0.508) 45 0 ?8 typ .008 ?.010 (0.203 ?0.254) so8 0303 .053 ?.069 (1.346 ?1.752) .014 ?.019 (0.355 ?0.483) typ .004 ?.010 (0.101 ?0.254) .050 (1.270) bsc 1 2 3 4 .150 ?.157 (3.810 ?3.988) note 3 8 7 6 5 .189 ?.197 (4.801 ?5.004) note 3 .228 ?.244 (5.791 ?6.197) .245 min .160 .005 recommended solder pad layout .045 .005 .050 bsc .030 .005 typ inches (millimeters) note: 1. dimensions in 2. drawing not to scale 3. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .006" (0.15mm) s8 package 8-lead plastic small outline (narrow .150 inch) (reference ltc dwg # 05-08-1610)
lt1809/lt1810 24 180910fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2000 lt 0709 rev a ? printed in usa related parts typical application single 3v supply, 4mhz, 4th order butterworth filter bene? ting from a low voltage supply operation, low dis- tortion and rail-to-rail output of lt1809, a low distortion ? lter that is suitable for antialiasing can be built as shown in figure 10. on a 3v supply, the ? lter has a passband of 4mhz with 2.5v p-p signal and a stopband that is greater than 70db to frequency of 100mhz. figure 10. single 3v supply, 4mhz, 4th order butterworth filter figure 11. filter frequency response + C v s 2 47pf 1/2 lt1810 220pf 665 v in v out 1809 f10 232 232 + C 22pf 470pf 562 274 274 1/2 lt1810 frequency (hz) 10k 100k 1m 10m 100m gain (db) 1809 f11 10 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 v s = 3v, 0v v in = 2.5v p-p part number description comments lt1395 400mhz current feedback ampli? er 800v/s slew rate, shutdown lt1632/lt1633 dual/quad 45mhz, 45v/s rail-to-rail input and output op amps high dc accuracy, 1.35mv v os(max) , 70ma output current, max supply current 5.2ma per ampli? er lt1630/lt1631 dual/quad 30mhz, 10v/s rail-to-rail input and output op amps high dc accuracy, 525v v os(max) , 70ma output current, max supply current 4.4ma per ampli? er lt1806/lt1807 single/dual 325mhz, 140v/s rail-to-rail input and output op amps high dc accuracy, 550v v os(max) , low noise 3.5nv/ hz , low distortion C80dbc at 5mhz

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